Technology scaling has provided enormous growth opportunities for the information and communication industry over the last few decades. It enables faster and cheaper products that deeply touch people’s life. Technology scaling is also crucial in improving energy efficiency, a hot topic lately as users demand ubiquitous computing and communications with minimum impact to the environment. In this presentation I will highlight research at Intel Labs spanning circuits, architecture, and platform to scale technology for energy efficiency. I will also discuss the associated scaling challenges, such as variations, resiliency, memory, I/O, security, power delivery, and power management. I will address them holistically by deriving solutions from a system perspective.
Dr. Wen-Hann Wang is Vice President of Intel Labs and Director of Circuits and Systems Research. He oversees research programs in Circuits, Systems, Security, and Electro-Photonics. Dr. Wang received his Ph.D. in Computer Science from University of Washington. Before joining Intel in 1991 Dr. Wang was a Research Staff Member at IBM T.J. Watson Research Center. Dr. Wang is an IEEE Fellow. He was granted 15 patents and received the inaugural IEEE/ACM ISCA Influential Paper Award and 1990 ACM SIGMETRICS best paper award.
Energy and power constraints have emerged as one of the greatest lingering challenges to progress in the computing industry. In this talk, I will highlight some of the "rules" of low-power design and show how they bind the creativity and productivity of architects and designers. I believe the best way to deal with these rules is to disregard them, through innovative design solutions that abandon traditional design methodologies. Releasing oneself from these ties is not as hard as one might think. To support my case, I will highlight two rule-breaking design technologies from my work. The first technique (Razor) combines low-power designs with resiliency mechanisms to craft highly introspective and efficient systems. The second technique (Subliminal) embraces subthreshold voltage design, which holds great promise for highly energy efficient systems.
Todd Austin is a Professor of Electrical Engineering and Computer Science at the University of Michigan in Ann Arbor. His research interests include computer architecture, robust system design, hardware and software verification, and performance analysis tools and techniques. Prior to joining academia, Todd was a Senior Computer Architect in Intel's Microcomputer Research Labs, a product-oriented research laboratory in Hillsboro, Oregon. Todd is the first to take credit (but the last to accept blame) for creating the SimpleScalar Tool Set, a popular collection of computer architecture performance analysis tools. Todd is co-author (with Andrew Tanenbaum) of the undergraduate computer architecture textbook, "Structured Computer Architecture, 6th Ed." In addition to his work in academia, Todd is founder and President of SimpleScalar LLC and co-founder of InTempo Design LLC. In 2002, Todd was a Sloan Research Fellow, and in 2007 he received the ACM Maurice Wilkes Award for "innovative contributions in Computer Architecture including the SimpleScalar Toolkit and the DIVA and Razor architectures." Todd received his PhD in Computer Science from the University of Wisconsin in 1996.
Every integrated circuit is released with latent bugs. The damage and risk implied by an escaped bug ranges from almost imperceptible to potential tragedy; unfortunately it is impossible to discern within this range before a bug has been exposed and analyzed. While the past few decades have witnessed significant efforts to improve verification methodology for hardware systems, these efforts have been far outstripped by the massive complexity of modern digital designs, leading to product releases for which an always smaller fraction of system's state has been verified. The news of escaped bugs in large market designs and safety critical domains is alarming because of safety and cost implications (due to replacements, lawsuits, etc.).
This talk will present some of our solutions to solve the verification challenge, such that users of future designs can be assured that their devices will operate completely free of bugs. We will attack the problem both at design-time, with statistical techniques to be deployed during post-silicon validation; and after deployment in the field, discussing novel solutions which can correct escaped bugs after a system has been shipped.
Valeria Bertacco is an Associate Professor of Electrical Engineering and Computer Science at the University of Michigan. Her research interests are in the area of design correctness, with emphasis on digital system reliability, post-silicon and runtime validation, and hardware- security assurance. Valeria joined the faculty at the University of Michigan in 2003, after being in the Advanced Technology Group of Synopsys for four years as a lead developer of Vera and Magellan. During the Winter of 2012, she was on sabbatical at the Addis Ababa Institute of Technology.
Valeria is the author of three books on design errors and validation. She received her M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1998 and 2003, respectively; and a Computer Engineering degree ("Dottore in Ingegneria") summa cum laude from the University of Padova, Italy in 1995. Valeria is the recipient of the IEEE CEDA Early Career Award, NSF CAREER award, the Air Force Office of Scientific Research's Young Investigator award, the IBM Faculty Award and the Vulcans Education Excellence Award from the University of Michigan.
It’s extremely difficult to store information or keep time without power. As embedded systems continue to shrink in size and energy consumption, batteries become the greatest hurdle to further optimization. In this talk, I will describe my recent research results on low-power computers. This work consists of three systems: stochastic storage on Half-Wits (USENIX FAST’11), time estimation based on memory decay (USENIX Security’12), and secure backscatter communication (USENIX Security’09).
The Half-Wits work analyzes the stochastic behavior of writing to embedded flash memory at voltages lower than recommended by a microcontroller’s specifications to reduce energy consumption. Flash memory integrated within a microcontroller typically requires the entire chip to operate on common supply voltage almost double what the CPU portion requires. Our approach tolerates a lower supply voltage so that the CPU may operate in a more energy efficient manner. Our software-only coding algorithms enable reliable storage at low voltages on unmodified hardware by exploiting the electrically cumulative nature of half-written data in write-once bits. Measurements show that our software approach reduces energy consumption by up to 50%. This work is joint with Erik Learned-Miller (UMass Amherst) and Andrew Jiang (Texas A&M).
The TARDIS technique helps locally maintain a sense of time elapsed without power and without special-purpose hardware. The TARDIS software computes the expiration state of a timer by analyzing the decay of existing on-chip SRAM. The TARDIS enables coarse-grained, hourglass-like timers such that cryptographic software can more deliberately decide how to throttle its response rate. Our experiments demonstrate that the TARDIS can measure time ranging from seconds to several hours depending on hardware parameters. Key challenges to implementing a practical TARDIS include compensating for temperature and handling variation across hardware. This work is joint with Wayne Burleson (UMass Amherst) and Jacob Sorber (Clemson University).
The CCCP work exploits radio as a resource to amplify the storage capabilities of batteryless, programmable RFID tags. The smaller energy requirements of radio allow the RFID tags either to devote more energy to computation or to accomplish the same tasks using less energy, which may translate into a longer operating range. The main challenge in this work is to design an energy-saving remote storage system that provides security under the constraints of passive RFID systems. Our experiments show that—despite cryptographic overhead—remote storage consumes less energy than storing data to flash for data sizes above roughly 64 bytes.
Mastooreh (Negin) Salajegheh is a postdoctoral research associate at the University of Virginia working with Dr. Kevin Skadron. She received her Ph.D. degree in 2012 from the University of Massachusetts Amherst, under the supervision of Dr. Kevin Fu. During her internship with Dr. Jie Liu's Sensing and Energy Research Group (SERG) at Microsoft Research, Negin researched trustworthy operation of Near Field Communication (NFC). She has received the Outstanding Synthesis Project award (Sponsored by Yahoo) for her work on probabilistic storage. Negin was one of the top four finalists of UMass Innovation Challenge Award. Her research focuses on low-power and trustworthy operation of pervasive computers, energy management, and probabilistic storage. Her research goal is to make low-power computers (specially batteryless ones) more energy-aware and more robust. During her PhD studies, Negin served as the co-chair of CS Women group at UMass Amherst for a year and she has attended several outreach events for girls in IT.
The rapid expansion of elderly population and increasing costs associated with chronic disease management demand novel technological solutions that shift healthcare services from clinical and hospital settings to a remote and home-bound scenario. Fortunately, the last decade has witnessed rapid advances in several technological domains including electronics, communications, and sensor design leading to the development of new remote health monitoring systems capable of collecting and analyzing varying heterogeneous physiological signals from human subjects. These systems promise to reduce healthcare costs and improve quality of life by reducing the morbidity, mortality, and economic costs associated with hospital readmissions due to various chronic diseases. The development of effective and sustainable remote health monitoring systems, however, faces a number of challenges regarding their robustness, scalability, power efficiency, and real-time responsiveness. This talk presents an end-to-end research methodology for design and development of next generation remote health monitoring platforms, with a particular emphasis on their data analytics and clinical validation. A data-driven system design approach is described to enhance power efficiency and usability of these systems while improving medical outcomes. Results on several ongoing research projects are introduced for optimal sensor selection and placement using wireless medical sensor nodes.
Hassan Ghasemzadeh is currently a Research Manager at the UCLA Wireless Health Institute and an Adjunct Professor of Biomedical Informatics at San Diego State University. His research interests lie in different aspects of Embedded System Design including sustainable and green computing, low-power architectures, reconfigurable computing, and system-level optimization. The focus of his current work is on processing platform design, collaborative signal and information processing, power optimization, data analytics, and algorithm design for networked embedded systems with a primary emphasis on applications in healthcare and wellness. His research spans the areas of embedded systems, computer architecture, signal processing, wireless networking, and machine learning, where he has published more than 70 technical papers on the subject including some the earliest works in the field that address fundamental challenges of next generation biomedical systems.
Hassan is currently leading several research projects funded by NSF, NIH, and industry, is an investigator on several funded proposals, and is a technology lead on many clinical studies. In 2011, he was honored as the Faculty of the Year for his contributions to the Biomedical Informatics program at SDSU. Hassan was the Founding Chair of the Computer Science Department at Azad University, Damavand Branch, Iran, between 2003 and 2006. In the past, he has received several awards including a best poster award from ACM HotMobile 2009, and a best paper award from IEEE RTAS 2011. He received his Ph.D. degree in Computer Engineering from the University of Texas at Dallas in 2010, and spent the academic year 2010-2011 as a Postdoctoral Fellow at the West Health Institute. He received his M.S. degree in Computer Engineering from University of Tehran, Tehran, Iran, in 2001 and his B.S. degree in Computer Engineering from Sharif University of Technology, Tehran, Iran in 1998.
Managing the energy consumption of computing devices is of critical importance given the limited battery lifetime of mobile platforms, and the increasing carbon footprint of mains powered PCs and servers. Traditional mechanisms to save energy such as shutting down (or duty-cycling) either individual subsystems or entire platforms do not work well in practice since they often come at the cost of usability or loss of functionality. In the first part of my talk, I will show that we can improve energy efficiency through system architectures that seek to design and exploit “collaboration” among heterogeneous but functionally similar subsystems. Using collaboration, individual subsystems or even entire platforms can be shut down more aggressively to reduce their energy usage. I have built several systems that exploit this central idea to demonstrate energy savings across a broad class of devices, and in this talk I will show its application in reducing PC energy usage by 70% on average.
While computing is indeed part of the problem due to its increasing carbon footprint, in the second part of my talk, I will show that computing is also part of the solution, where it can be used to make other systems more energy efficient. In particular, I will focus on sensing and control solutions that we have designed and deployed within enterprise buildings to make them more energy efficient and sustainable. I will show that by using fine-grained occupancy information gathered from battery powered wireless sensors the energy consumption of the HVAC system within a building can be reduced dramatically, saving up to 40% in a test deployment. I will also describe our smart energy meter that can measure the energy usage of plug-loads within a building as well as provide a mechanism to control these loads based on a number of policies.
Yuvraj Agarwal is a Research Scientist in the Department of Computer Science and Engineering at the University of California San Diego, where he also completed his PhD. His research interests are at the intersection of Systems and Networking and Embedded Systems, and he is particularly interested in research problems that benefit from using hardware insights to build more scalable and efficient systems. In recent years, his work has focused on Green Computing, Mobile Computing, Privacy and Energy Efficient Buildings. In 2012, he was awarded the "Outstanding Faculty Award for Sustainability" given by the UCSD Chancellor. He is a member of the IEEE, ACM and USENIX.
Multicore scaling — increasing the number of cores per die each generation—is currently the principal strategy of the microprocessor industry for continuing performance growth. As I will present in this talk, the results of our dark silicon study show that core count scaling will not provide the performance and value needed to scale down many more technology generations. This impending end of continued performance scaling and the looming end of Moore’s Law will be disruptive for the entire computing community. Significant departures from conventional approaches are needed to provide continued performance and efficiency gains in general-purpose computing. I will talk about general-purpose approximate computing as a new possible direction. I will then present a new class of accelerators, called Neural Processing Units. NPUs leverage an approximate algorithmic transformation that converts regions of code from a Von Neumann model to a neural model. Our work shows significant gains when the abstraction of full precision is relaxed in general-purpose computing and opens new venues for research.
Hadi Esmaeilzadeh is a Ph.D. candidate in the Department of Computer Science and Engineering at University of Washington. He has a master’s degree in Computer Science from The University of Texas at Austin and a master’s degree in Electrical and Computer Engineering from University of Tehran. Hadi is interested in developing new technologies and cross-stack solutions to improve the performance and energy efficiency of computer systems for emerging applications.
Big data is revolutionizing the way we live, work, and socialize. At the same time, big data is taxing our compute infrastructure in unprecedented ways. In many domains, data expansion rates are dwarfing the pace of technology improvement as measured by Moore’s law, challenging our ability to effectively store and process the data. Moreover, with the hardware industry hitting fundamental limits on its ability to lower operating voltages, energy requirements in big-data applications are skyrocketing. Sustaining the pressure of big data, and delivering on its promises, requires a fundamental restructuring of our compute infrastructure for data scalability. In this talk, I will focus on data-intensive online applications, such as web search and social connectivity. I will explain how the mismatch between application demands and existing processor architectures leads to significant inefficiencies at the datacenter level. As a first step toward data-scalable systems, I will describe Scale-Out Processors, a processor design methodology and microarchitectural support for data-intensive online processing. By tuning the processor organization to the needs of the application domain, Scale-Out Processors improve datacenter performance by over 7x within a fixed power budget versus state-of-the-art server processors.
Boris Grot is a post-doctoral researcher in the Parallel Systems Architecture Lab at EPFL. His research seeks to address efficiency bottlenecks and capability shortcomings of processing platforms for big data. Grot received his PhD in Computer Science from The University of Texas at Austin in 2011.
Power has become a first-class design constraint in computing platforms from the smartphone in your pocket to warehouse-scale computers in the cloud. Historically, semiconductor innovation has repeatedly provided more transistors (Moore’s Law) for roughly constant power per chip by scaling down supply voltage each generation. Unfortunately voltage scaling has ended due to stability limits and chip power densities are increasing each generation on a trajectory that outstrips improvements in the ability to dissipate heat. To continue to extract value from Moore’s Law, we need to find system-level approaches to improve efficiency and deliver more performance within tight energy, power, and thermal constraints.
In the first part of this talk, I will discuss Computational Sprinting, a technique to improve the responsiveness of smartphone platforms by transiently exceeding sustainable thermal limits — firing up numerous `dark silicon’ cores to complete a sub-second burst of computation while buffering the resulting heat in a phase change material embedded in the chip’s heat sink. Then, I will shift focus to warehouse-scale computing to discuss power management in online data intensive services. These applications, such as web search, social networking, and ad serving, must process terabytes of data in interactive time scales, making them a challenging target for power management.
Thomas Wenisch is the Morris Wellman Faculty Development Assistant Professor of Computer Science and Engineering at the University of Michigan, specializing in computer architecture. Tom's prior research includes memory streaming for commercial server applications, store-wait-free multiprocessor memory systems, memory disaggregation, and rigorous sampling-based performance evaluation methodologies. His ongoing work focuses on computational sprinting, data center architecture, energy-efficient server design, and multi-core / multiprocessor memory systems. Tom received an NSF CAREER award in 2009, three papers selected in IEEE Micro Top Picks, and Best Paper Awards at HPCA 2012 and ISPASS 2012. Prior to his academic career, Tom was a software developer at American Power Conversion, where he worked on data center thermal topology estimation. He is co-inventor on six patents. Tom received his Ph.D. in Electrical and Computer Engineering from Carnegie Mellon University.
We stand at the brink of a major disruption in the semiconductor industry. Our inability now to manufacture more efficient transistors will inherently limit the scalability of future multi-core architectures. To unleash new capabilities in next-generation servers and devices, hardware specialization in the form of ASICs and FPGAs offers significant potential in enhancing processor efficiency by an order of magnitude or more. As a first step towards making specialization viable for the “masses”, this talk will present CoRAM, a joint effort with CMU to develop and prototype a scalable, portable, and programmable memory abstraction for future FPGAs. I will also discuss ongoing research efforts such as the LINQits project, a first step towards bridging the gulf between rich software ecosystems and low-level programmable logic.
Eric Chung is currently a post-doc at Microsoft Research Silicon Valley and received his PhD at Carnegie Mellon University in 2011. He is broadly interested in architecting hardware specialization for future computer architectures and software systems. In a collaboration with CMU, he leads the CoRAM project, an endeavor to build scalable portable FPGA architectures. He was also the lead developer of ProtoFlex, an architecture for emulating full-system, large-scale multiprocessors using FPGAs.
As we move closer to the digital society, the feasibility and sustainability of connected life becomes increasingly challenged and criticized. A large part of this criticism lies with the growing energy footprint of communications that threatens to slow the progress of networking. While scientists and research organizations have long paid attention to this problem, insofar the impact of academic research in this area had little traction with the industry. This growing gap between networkers, researchers and general public may have long-term impact on our society. This talk will offer an insight into this problem from the industry perspective. It will share industry’s views on the current and future environment-related problems in networking and silicon development. The talk is intended for the wide audience of computer scientists and electrical engineers interested in learning about the potential commercial and social impact of their work.
Daniel Kharitonov is a principal engineer at Juniper Networks, a leading manufacturer of routing and switching equipment. His primary background is in protocols development, with Engineering degree from St. Petersburg State Technical University and post-graduate education at Central Research Institute of Robotics and Cybernetics in Russia. Having joined Juniper in 2002, Dr. Kharitonov contributed to a number of critically acclaimed projects, including core and multichassis routing systems, edge and universal edge devices. Prior to joining Juniper, Dr. Kharitonov worked for a number of startups in supercomputing and data processing areas. On the green communications side, Mr. Kharitonov acted as a co-founder of ECR Initiative and later contributed to harmonization of metrics and test methodologies between study groups of study groups of ITU-T, ATIS, ETSI, Climate Savers Initiative and the Broadband Forum. He is an author or co-author of many publications on topics of energy efficiency in the data communications environment that appeared in the industry press, peer-reviewed journals and conference proceedings. In his free time, Mr. Kharitonov enjoys skiing, surfing and travel.
Recent advances in signal processing theory, algorithm design, and very-large scale integration (VLSI) are accelerating progress in a host of important applications, including signal processing, imaging, and wireless communication. Today’s key challenge for the VLSI designer is to realize increasingly complicated algorithms that process massive amounts of data using cost-effective, low-power circuits and systems.
In this talk, I will advocate a holistic design approach that jointly considers the theory, algorithms, and VLSI implementation aspects to master this challenge. To highlight the efficacy of this approach, I will present an example from my recent research on the design of a wideband analog-to-information (A2I) converter in 28nm CMOS technology. The proposed A2I converter performs simultaneous dimensionality reduction and acquisition of spectrally sparse wideband signals using a low-complexity random-subsampling analog-to-digital converter. A dedicated digital recovery unit then reconstructs the spectral information at high rates via convex optimization. I will demonstrate the capabilities of the proposed A2I converter design and discuss the pros and cons of compressive signal acquisition and sparse recovery from a VLSI implementation point-of-view.
Christoph Studer received his MS and PhD degrees in Information Technology and Electrical Engineering from ETH Zurich, in 2005 and 2009, respectively. In 2005, he was a Visiting Researcher with the Smart Antennas Research Group at Stanford University. From 2006 to 2009, he was a Research Assistant in both the Integrated Systems Laboratory (IIS) and the Communication Technology Laboratory (CTL) at ETH Zurich. From 2009 to 2012, Dr. Studer was a Postdoctoral Researcher at CTL, ETH Zurich, and in the Digital Signal Processing Group at Rice University. Since 2013, he has held the position of Research Scientist at Rice University. Dr. Studer's research interests include the design of digital VLSI circuits and systems, signal and image processing, analysis of massive datasets, and wireless communication.
Dr. Studer was the recipient of an ETH Medal in 2005 and 2011 for his MS and PhD theses, respectively. He has received best student paper awards at the 2007 Asilomar Conference on Signals, Systems, and Computers and the 2008 IEEE International Symposium on Circuits and Systems, and received the 2010 Swisscom/ICTnet Innovations Award. In 2011, Dr. Studer was awarded a two-year fellowship for Advanced Researchers by the Swiss National Science Foundation (SNSF).
Systems-on-a-chip in client devices like cell phones has a lot of specialized hardware to reduce power/energy consumption. In this brave new world, the whole software stack must interface with ever changing hardware at the bottom. Such systems by definition are highly concurrent and reactive. A method of building such systems is to compose functionally specialized modules, be they are implemented in hardware or software, in a manner that the functionality and performance of the system is predictable from the parts. We will present a hardware inspired methodology for concurrent and parallel programming and show how it can be used to automatically generate hardware/software interfaces and the associated communication infrastructure.
Arvind is the Johnson Professor of Computer Science and Engineering at MIT. Arvind’s group, in collaboration with Motorola, built the Monsoon dataflow machines and its associated software in the late eighties. In 2000, Arvind started Sandburst which was sold to Broadcom in 2006. In 2003, Arvind co-founded Bluespec Inc., an EDA company to produce a set of tools for high-level synthesis. In 2001, Dr. R. S. Nikhil and Arvind published the book "Implicit parallel programming in pH". Arvind's current research focus is on enabling rapid development of embedded systems. Arvind is a Fellow of IEEE and ACM, a member of the National Academy of Engineering and a Fellow of the American Academy of Arts and Sciences.
This talk presents several novel methodologies to facilitate large-scale modeling for complex systems. Our work is motivated by the emerging need of large-scale statistical performance modeling for analog and mixed-signal integrated circuits (ICs). The objective is to capture the impact of process and environmental variations for today’s nanoscale circuits. In particular, we explore a number of novel statistical techniques (e.g., sparse regression, model fusion, etc) to address the modeling challenges posed by high dimensionality and strong nonlinearity. As such, the parametric yield of nanoscale ICs can be predicted both accurately and efficiently. This talk also discusses how the proposed modeling techniques can be further applied to adaptive post-silicon tuning of analog and mixed-signal circuits.
In addition, our algorithms originally developed for VLSI CAD problems have been successfully extended to other non-CAD applications. The second part of this talk briefly discusses a clinical application of brain computer interface based on magnetoencephalography (MEG). The objective of BCI is to provide a direct control pathway from brain to external devices. We will show how statistical modeling algorithms can be applied to improve the signal-to-noise ratio of MEG recording.
Xin Li received the Ph.D. degree in Electrical and Computer Engineering from Carnegie Mellon University, Pittsburgh, PA in 2005, and the M.S. and B.S. degrees in Electronics Engineering from Fudan University, Shanghai, China in 2001 and 1998, respectively. He is currently an Assistant Professor in the Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA. In 2005, he co-founded Xigmix Inc. to commercialize his PhD research, and served as the Chief Technical Officer until the company was acquired by Extreme DA in 2007. In 2011, Extreme DA was further acquired by Synopsis (Nasdaq: SNPS). Since 2009, he has been appointed as the Assistant Director for FCRP Focus Research Center for Circuit & System Solutions (C2S2). His research interests include computer-aided design, neural signal processing, and power system analysis and design.
Dr. Xin Li has been an Associated Editor of IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD) since 2012 and an Associated Editor of Journal of Low Power Electronics (JOLPE) since 2011. He served on the Technical Program Committee of Design Automation Conference (DAC) from 2011 to 2012, the Technical Program Committee of International Conference on Computer-Aided Design (ICCAD) from 2008 to 2011, the Technical Program Committee of International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU) from 2010 to 2012, the Technical Program Committee of International Conference on VLSI Design (VLSI) in 2009, and the IEEE Outstanding Young Author Award Selection Committee in 2006. He received the NSF Faculty Early Career Development Award (CAREER) in 2012, a Best Paper Award from Design Automation Conference (DAC) in 2010 and two IEEE/ACM William J. McCalla ICCAD Best Paper Awards in 2004 and 2011.
Todd Austin, Professor, U. of MI
"On the Rules of Low Power Design (and Why You Should Break Them)"
Valeria Bertacco, Assoc Prof, U. MI
"Multicore processors: will we ever get them right?"
Mastooreh (Negin) Salajegheh, UVA
"Low-power Embedded Computing at the Limits of Digital Abstraction"
Hassan Ghasemzadeh, UCLA
"Remote Health Monitoring: Saving the Healthcare System using Wireless Health"
Yuvraj Agarwal, UC San Diego
"From Energy Efficient Computing to Energy Efficient Buildings"
Hadi Esmaeilzadeh, U. of WA
"Approximate Acceleration for a Post-Multicore Era"
Boris Grot, EPFL
"Toward Data-Scalable Systems"
Eric Chung, Microsoft Research
"CoRAM and Beyond: Towards Logic Specialization for the Masses"
Thomas Wenisch, Prof, U of MI
"Power Management from Smartphones to Data Centers"
Daniel Kharitonov, Juniper Ntwks
"Modern Problems in Green Communications"
Christoph Studer, Rice U.
"Wideband Analog-to-Information Conversion: From Theory to VLSI Circuits"
Arvind, Professor, MIT
"Programming in the Brave New world of Systems-on-a-chip"
Xin Li, Asst Prof, Carnegie Mellon U
"Large-scale Modeling for Complex Systems: Bridging VLSI CAD Algorithms with Clinical Applications"